1. Field of the Invention
The present invention generally relates to an electrically erasable and programmable non-volatile semiconductor memory device and a manufacturing method of the same, and particularly relates to an improved structure of a so-called flash memory (electrically erasable and programmable read only memory) allowing electrical batch erase of electric charges for written information and to an improved manufacturing method of the same.
2. Description of the Background Art
EEPROMs are memory devices having structure capable of free programming of data as well as electrical writing and erasing. U.S. Pat. No. 4,868,619 and "An In-System Reprogrammable 32K.times.8 CMOS Flash Memory" by Virgil Niles Kynett, et al (IEEE Journal of Solid-State Circuits, Vol. 23, No. 5, October 1988) have disclosed a flash memory, i.e., an EEPROM formed of one transistor and allowing electrical batch erase of written information charges.
FIG. 19 is a block diagram showing a general construction of a flash memory. In the figure, the EEPROM includes a memory cell matrix including rows and columns, an X-address decoder 200, a Y-gate sense amplifier 300, a Y-address decoder 400, an address buffer 500, I/O (input/output) buffer 600 and a control logic 700. Memory cell matrix 100 includes a plurality of memory transistors arranged in rows and columns. The rows and columns of memory cell matrix 100 are selected by X-address decoder 200 and Y-gate sense amplifier 300 connected thereto. Y-gate sense amplifier 300 is connected to Y-address decoder 400 for applying information for selecting the columns. X-address decoder 200 and Y-address decoder 400 are connected to address buffer 500 which temporarily stores address information. Y-gate sense amplifier 300 is connected to I/O buffer 600 which temporarily stores I/O data. Address buffer 500 and I/O buffer 600 are connected to control logic 700 which controls an operation of the flash memory. Control logic 700 performs the control operation based on a chip enable signal, an output enable signal and a program signal.
FIG. 20 is an equivalent circuit diagram showing a general construction of memory cell matrix 100 shown in FIG. 19. In the figure, there are disposed word lines WL.sub.1, WL.sub.2, . . . , WL.sub.i extending in a row direction and bit lines BL.sub.1, BL.sub.2, . . . , BL.sub.i which extend in a column direction and intersect the word lines to form a matrix. Memory transistors Q.sub.11, Q.sub.12, . . . , Q.sub.ii each having a floating gate are disposed at intersections between the word lines and the bit lines. Each memory transistor has a drain connected to the bit line and a control gate connected to the word line. Sources of the memory transistors are connected to source lines S.sub.1, S.sub.2, . . . , respectively. The sources of the memory transistors belonging to the same row are mutually connected, as shown in the figure, and are also connected to source lines S.sub.1, S.sub.2, . . . located at the opposite sides thereof. The source lines of all the memory cells are connected to each other in order to allow batch erasing.
FIG. 21 is a partial cross section showing a sectional structure of one memory transistor forming a part of the flash memory described above. The EEPROM shown in FIG. 21 is called as a stack gate type EEPROM. FIG. 22 is a schematic plan view showing a plane layout of the stack gate type flash memory of the prior art. FIG. 23 is a partial cross section taken along line XXIII--XXIII in FIG. 22. Referring to these figures, the construction of the conventional flash memory will be described below.
Referring to FIGS. 21 and 23, a p-type silicon substrate 1 has a main surface on which n-type impurity regions, e.g., n.sup.+ -drain diffusion regions 32 and n.sup.+ -source diffusion regions 33 are formed with spaces therebetween. Control gate electrodes 37 and floating gate electrodes 35 are formed in regions between n.sup.+ -drain diffusion regions 32 and n.sup.+ -source diffusion regions 33 for forming channel regions. Floating gates electrode 35 are formed on silicon substrate 1 and a thin gate oxide film 34 having a thickness of about 100.ANG. is formed therebetween. Control gate electrodes 37 are electrically isolated from floating gate electrodes 35 by layer insulating films 36 formed on the floating gate electrodes 35. Floating gate electrodes 35 and control gate electrodes 37 are formed of polysilicon layers. A thermally oxidized film 38 is formed by thermal oxidation of a surface of the polysilicon layers which form floating gate electrodes 35 and control gate electrodes 37. Floating gate electrodes 35 and control gate electrodes 37 are covered by a smooth coating film 12 formed of, e.g., an oxide film.
As shown in FIG. 22, control gate electrodes 37 are mutually connected to form the word lines extending in a lateral direction, i.e., row direction. Bit lines 13 are perpendicular to the word lines 37 and interconnect n.sup.+ -drain diffusion regions 32 arranged in a longitudinal direction, i.e., column direction. Bit lines 13 electrically contact n.sup.+ -drain diffusion regions 32 through drain contacts 15, respectively. As shown in FIG. 23, bit lines 13 are formed on smooth coating film 12. As shown in FIG. 22, each n.sup.+ -source diffusion region 33 extends along word lines 37, and is formed in the region surrounded by word lines 37 and field oxide films 10. Each n.sup.+ -drain diffusion region 32 is formed in a region surrounded by word lines 37 and field oxide films 10.
An operation of the flash memory thus constructed will be described below with reference to FIG. 21.
In a writing operation, a voltage V.sub.D of about 6-8V is applied to n.sup.+ -drain diffusion region 32 and a voltage V.sub.G of about 10-15V is applied to control gate electrode 37. Applied voltages V.sub.D and V.sub.G cause an avalanche break-down phenomenon at the vicinities of n.sup.+ -drain diffusion region 32 and gate oxide film 34. This generates electrons having high energies at the vicinities of the same. Some of these electrons are attracted to floating gate electrode 35, as shown by an arrow 1, by an electric field caused by voltage V.sub.G which is applied to control gate electrode 37. The electrons are accumulated in floating gate electrode 35 in this manner, so that a threshold voltage V.sub.th of the control gate transistor increases. The state in which threshold voltage V.sub.th increases above a predetermined value is called as a written state "0".
Then, in an erasing operation, a voltage V.sub.S of about 10-12V is applied to n.sup.+ -source diffusion region 33, and a ground potential is maintained in control gate electrode 37 and n.sup.+ -drain diffusion region 33. Since an electric field caused by voltage V.sub.S is applied to n.sup.+ -source diffusion region 33, the electrons in floating gate electrode 35 pass, as shown by an arrow 2, through thin gate oxide film 34 owing to a tunnel effect. In this manner, the electrons in the floating gate electrode 35 are extracted, so that threshold voltage V.sub.th of the control gate transistor decreases. A state in which threshold voltage V.sub.th is lower than the predetermined value is called as an erased state "1". Since the source regions of the memory transistors are mutually connected, as shown in FIG. 20, this erasing operation causes batch erase for all the memory cells.
In a reading operation, a voltage V.sub.G, of about 5V is applied to control gate electrode 37, and a voltage V.sub.D, of about 1-2V is applied to n.sup.+ -drain diffusion region 32. In this operation, the above mentioned states "1" and "0" are determined, based on the existence of the current flowing through the channel region of the control gate transistor, i.e., based on the actual state between the ON and OFF states of the control gate transistor.
In the stack gate type flash memory of the prior art, gate oxide film 34 is formed of the thin oxide film having the thickness of about 100.ANG. for generating the tunnel effect. This is preferable for the erasing operation of the data, but unpreferably deteriorates a writing property or characteristic for the data in the writing operation.
In the erasing operation, the tunnel effect generates only at the vicinity of n.sup.+ -source diffusion region 33 and gate oxide film 34. However, gate oxide film 34 in the conventional EEPROM is entirely formed of the thin oxide film having the thickness of about 100.ANG.. Therefore, it is necessary to form the thin oxide film, which requires high quality, over an excessively large area. These problems will be further detailed below.
In the writing operation of the memory transistor in the stack gate type EEPROM, voltage V.sub.G is applied to the control gate electrode 37. Voltage V.sub.G is divided into voltages V.sub.1 and V.sub.2 in accordance with capacities of capacitors C.sub.1 and C.sub.2. Capacitor C.sub.1 is formed of control gate electrode 37, layer insulating film 36 and floating gate electrode 35. Capacitor C.sub.2 is formed of floating gate electrode 35, gate oxide film 34 and silicon substrate 1. The writing efficiency is determined by divided voltage V.sub.2 applied to capacitor C.sub.2, because higher voltage V.sub.2 promotes the avalanche break-down phenomenon generating between n.sup.+ -source diffusion region 33 and n.sup.+ -drain diffusion region 32, by which more electrons are implanted into floating gate electrode 35. In this operation, V.sub.2 is given by a following equation. ##EQU1##
Therefore, capacitor C.sub.2 having a smaller capacity is required to obtain larger voltage V.sub.2. In the memory transistor of the conventional stack gate type EEPROM, however, reduction of the thickness of gate oxide film 34 increases the capacity of capacitor C.sub.2, and thus deteriorates the writing property in the conventional construction of the memory transistor.
Meanwhile, in the erasing operation, high V.sub.S of 10V or more is applied to n.sup.+ -source diffusion region 33 so that the electrons are extracted from the floating gate electrode 35 owing to the tunnel effect as described above. The high electric field of about 10-12MV/cm required for causing the tunnel effect is generated only at the vicinity of n.sup.+ -source diffusion region 33 and gate oxide film 34. Therefore, gate oxide film 34 having the small thickness of about 100.ANG. is not required at regions other than those at which the high electric field is generated. A critical standard of quality control is required in processes for forming the oxide film in order to excessively enlarge the regions in which the oxide film having a controlled thin film is formed.
In the conventional construction of the stack gate type EEPROM, floating gate electrode 35 and control gate electrode 37 occupy a predetermined plane area through which they overlap each other. Therefore, the region of each memory cell is determined by an area occupied by n.sup.+ -drain diffusion region 32, n.sup.+ -source diffusion region 33 and floating gate electrode 35. Consequently, as long as the construction of the memory transistor shown in FIG. 21 is employed, dimensions of the memory cell can be reduced to a restricted extent, and in practice, it is difficult to reduce the dimensions of the memory cell.